Overview

Silicon Library (SLI) HDMI 2.0 RX IP solution, which consists of PHY analog IP and digital LINK IP, is compliant with HDMI 2.0b standard. PHY analog IP is provided as a hard macro and LINK IP is provided as a soft macro including synthesizable RTL code. SLI HDMI 2.0 RX PHY IP consists of three data channels, one clock channel and a clock multiplier PLL, and it supports the data rate up to 6Gbps per channel. LINK IP includes HDCP compliant with 2.2 / 1.4. The combination of SLI’s PHY IP and LINK IP ensures that customers easily and securely implement HDMI interface to SoCs.

PHY Features

• HDMI 2.0b standard compliant physical layer
• Up to 6Gbps/ch for 4K2K 60fps
• Programmable Equalizer Strength
• Programmable on-chip termination resistor
• Programable analog characteristics
• Test / Debug modes

LINK Features

• HDMI 2.0b standard compliant LINK layer
• HDCP compliant with 2.2 / 1.4
• Color space conversion
• Supports deep colors
• Audio interface

Availability

This PHY IP is available as Silicon proven ‘off-the-shelf’ IP in TSMC40nm. Please download the product brief or contact sales for more detailed information. SLI will accept porting requests from customers.