General Description

Silicon Library (SLI) SDHC/SDXC UHS-II PHY IP solution, which consists of analog PHY IP module and digital Physical Coding Sublayer (PCS) IP module, is compliant with SD 4.1 standard. PHY analog IP is provided as a hard macro, and PCS IP is provided as a synthesizable soft macro.

SLI UHS-II PHY Analog IP consists of a mixed-signal SERDES supporting both Full Duplex and Half Duplex modes. The data rate covers from 390Mbps to 1.56Gbps (Full Duplex) / 3.12Gbps (Half Duplex). This IP can be configured as either Host applications such as DSC and SD Card readers, or Device applications including SD Cards.SLI UHS-II PCS IP supports both 8bit and 16bit interfaces for the link layer to provide the flexibility of user implementation. Loopback modes, Built-In-Self-Test (BIST) and other test modes are available for customer’s SoC and system tests.

PHY Features

• SD 4.1 standard compliant physical layer
• Support either UHS-II host or device
• 156MB/s (Full-Duplex), 312MB/s (Half-Duplex)
• Programable analog characteristics

PCS Features

• SD 4.1 standard compliant physical coding sublayer
• Fully synthesizable RTL
• 8bit and 16bit interfaces with link layer
• Power saving modes
• Test mode control
• Analog characteristics control

Availability

This IP is available as Silicon proven ‘off-the-shelf’ IP in various major fabs and technology nodes from 6nm to 130nm. Please download the product brief or contact sales for more detailed information. SLI will accept porting requests from customers.