Overview

Silicon Library (SLI) MIPI® D-PHY RX IP is a complete PHY solution that is fully compliant to MIPI D-PHY specification version 1.2, enabling easy integration of MIPI® D-PHY interface into low-power modern SoCs. The solution consists of Analog PHY and digital Control and Interface Logic (CIL). PHY is provided as a hard macro while CIL is provided as a synthesizable soft macro. This IP solution can be applied to both MIPI® Camera Serial Interface (CSI-2) and MIPI® Display Serial Interface (DSI) protocols. Both High-Speed (HS) and Low-Power (LP) modes are supported with one clock lane and four data lanes.

Features

• Compliant with MIPI® D-PHY specification version 1.2
• One clock lane and four data lanes
• PHY Protocol Interface (PPI)
• Supports synchronous data transfer in high speed (HS) mode, covering 80M-1.5Gbps
• Supports asynchronous data communication in low power (LP) mode at up to 10Mbps
• Configurable skew adjustment
• Supports Ultra-Low Power State
• Sequence error detection mechanism

Availability

This PHY IP is available as Silicon proven ‘off-the-shelf’ IP in major fabs and technology nodes of 22nm and 55nm. Please download the product brief or contact sales for more detailed information. SLI will accept porting requests from customers.