Overview

This USB3.0 PCIe2.0 Combo PHY IP is a complete physical layer (PHY) IP solution, supporting both USB3.0 and PCI Express2.0. The PHY IP integrates mixed-signal circuits to support 2.5G and 5.0G data rate. It consists of both the PMA layer and the PCS

Features

• Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer
• Supports 2.5GT/s and 5.0GT/s serial data transmission rate
• Supports 16-bit or 32-bit parallel interface
• Data and clock recovery from serial stream
• 8b/10b encoder/decoder and error indication
• Support direct disparity control for use in transmitting compliance pattern in Pole mode
• Support power change and rate change at a same PCLK edge in PCIe mode
• Tunable Receiver detection to detect worse case cables
• Beacon transmission and reception in Pole mode
• Low Frequency Periodic Signaling (LFPS) transmission and reception in USB3.0 mode
• Support SSCG function to reduce EMI effects with tunable down-spread amplitude
• Selectable TX margining, Tx de-emphasis and signal swing values
• Internal Loopback Test Capable
• Allowable analog circuit parameter adjustment and internal test control
• Compliant with USB3/PCIe base specification