Overview

Silicon Library (SLI) DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4b TX IP cores provide a comprehensive transmitter solution compliant with VESA DisplayPort 1.4a and Embedded DisplayPort (eDP) 1.4b standards, enabling seamless integration into SoCs for modern multimedia applications. The solution consists of two modules: a physical layer (PHY) and a controller (Link Layer / PCS). The PHY is a hard macro supporting high-speed data rates up to 8.1Gbps (HBR3), while the controller is provided as a synthesizable soft macro. In addition to required DisplayPort functionalities, the solution supports optional features including Multi-Stream Transport (MST), Display Stream Compression (DSC), Forward Error Correction (FEC) and HDCP 1.4/2.3 Content Protections by its configurable controller. SLI’s PHY IPs and Controller IPs work together to deliver the best results with simplified integration although SLI’s PHY and Controller IPs can be offered as independent products .

PHY Features

• DP version 1.4a / eDP version 1.4b compliant transmitter
• Supports both SST and MST (up to 4 streams) modes
• Configurable (4/2/1) link channels and one AUX channel

• 1.62Gbps (RBR), 2.7Gbps (HBR), 5.4Gbps (HBR2), and 8.1Gbps (HBR3) per lane

  • ⇒ Also supports all recommended data rates (i.e. 2.16Gbps) defined in eDP v1.4b
• Programable pre-emphasis
• Programable analog characteristics
• Test modes including Loopback test, PLL test and DC test

Controller Features

• DP version 1.4a / eDP version 1.4b compliant transmitter
• Supports SST and optionally MST (up to 4 streams) modes

• Supports both video packet and audio packet

  • ⇒Supports all digital video output formats (RGB/YCbCr/RAW/Y-only)
  • ⇒Supports LPCM audio (up to 8ch) via I2S slave I/F
• Supports both Default and Enhanced Framing Modes
• Hardware link training management
• Hardware EDID reading via AUX CH
• Configuration registers programmable via AMBA APB interface
• Supports HDCP 1.4 / 2.3 (optional)
• Supports DSC and FEC (Rambus Inc) as options

Block diagram

Availability

This PHY IP is available as Silicon proven ‘off-the-shelf’ IP in various major fabs and technology nodes from 12nm to 55nm. Please download the product brief or contact sales for more detailed information. SLI will accept porting requests from customers.