USB3.1 Gen2 PHY


This USB3.1 Gen2 PHY IP implements a USB3.1 Gen2 transceiver for use with either host and device function controllers. It integrates mixed-signal circuits to support USB3.1 Gen2 high speed data rate up to 10Gbps and is backward compatible to Gen1 data rate at 5Gbps


  • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
  • Supports 5.0Gbps and 10Gbps serial data transmission rate
  • Supports 16-bit or 32-bit parallel interface
  • Data and clock recovery from serial stream
  • Support 8b/10b encoder/decoder(Gen1), 128/132 encoder/decoder(Gen2) and error indication
  • Tunable receiver detection to detect worse case cables
  • Low Frequency Periodic Signaling (LFPS) transmission and reception
  • Support SSCG function to reduce EMI effects with tunable down-spread amplitude
  • Selectable TX margining, TX de-emphasis and signal swing values
  • Built-in-self-test with internal Loopback test option
  • Programmable analog circuit parameter adjustment and internal test control
  • Compliant with USB3.1 Gen2 base specification